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? semiconductor components industries, llc, 2005 december, 2005 ? rev. 3 1 publication order number: NCV4279/d NCV4279 5.0 v micropower 150 ma ldo linear regulator with delay, adjustable reset, and sense output the NCV4279 is a 5.0 v precision micropower voltage regulator with an output current capability of 150 ma. the output voltage is accurate within 2.0% with a maximum dropout voltage of 0.5 v at 100 ma. low quiescent current is a feature drawing only 150 a with a 1.0 ma load. this part is ideal for any and all battery operated microprocessor equipment. microprocessor control logic includes an active reset output ro with delay and a si/so monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. the use of the si/so monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. the active reset circuit operates correctly at an output voltage as low as 1.0 v. the reset function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. the reset threshold voltage can be decreased by the connection of an external resistor divider to the r adj lead. the regulator is protected against reverse battery, short circuit, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. the device has also been optimized for emc conditions. if the application requires pullup resistors at the logic outputs reset and sense out, the ncv4269 with integrated resistors can be used. features ? 5.0 v 2.0% output ? low 150 a quiescent current ? active reset output low down to v q = 1.0 v ? adjustable reset threshold ? 150 ma output current capability ? fault protection ? +60 v peak transient voltage ? ?40 v reverse voltage ? short circuit ? thermal overload ? early warning through si/so leads ? internally fused leads in so?14 package ? very low dropout voltage ? electrical parameters guaranteed over entire temperature range ? pb?free packages are available ? ncv prefix for automotive and other applications requiring site and control changes http://onsemi.com so?14 d suffix case 751a 1 14 marking diagrams 1 NCV4279 awlywwg 14 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week , g = lead free indicators so?8 d suffix case 751 ordering information see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. 1 8 4279 alyw 1 8
NCV4279 http://onsemi.com 2 i ro q so r adj d figure 1. block diagram gnd si reference or error amplifier reference and trim current and saturation control + ? pin connections so ro q gnd gnd gnd gnd gnd 114 gnd gnd i d si r adj so?14 gnd d 18 ro r adj so si q i so?8 package pin description package pin number pin symbol function so?8 so?14 3 1 r adj reset threshold adjust; if not used to connect to gnd. 4 2 d reset delay; to set time delay, connect to gnd with a capacitor 5 3, 4, 5, 6, 10, 11, 12 gnd ground 6 7 ro reset output; this is an open?collector output. leave open if not used. 7 8 so sense output; this is an open?collector output. if not used, keep open. 8 9 q 5 v output; connect to gnd with a 10 f capacitor, esr < 10 . 1 13 i input; connect to gnd directly at the ic with a ceramic capacitor. 2 14 si sense input; if not used, connect to q.
NCV4279 http://onsemi.com 3 maximum ratings (t j = ?40 c to 150 c) parameter symbol min max unit input to regulator v i i i ?40 internally limited 45 internally limited v input peak transient voltage v i ? 60 v sense input v si i si ?40 ?1 45 1 v ma reset threshold adjust v radj i radj ?0.3 ?10 7 10 v ma reset delay v d i d ?0.3 internally limited 7 internally limited v ground i q 50 ? ma reset output v ro i ro ?0.3 internally limited 7 internally limited v sense output v so i so ?0.3 internally limited 7 internally limited v regulated output v q i q ?0.5 ?10 7.0 ? v ma junction temperature storage temperature t j t stg ? ?50 150 150 c c input voltage operating range junction temperature operating range v i t j ? ?40 45 150 v c junction?to?ambient thermal resistance so?8 so?14 r ja ? 200 70 k/w junction?to?pin 4, all gnd pins grounded. so?14 r jp ? 30 k/w lead temperature soldering and msl parameter symbol value unit msl, 8?lead, 14?lead, ls temperature 260 c peak (notes 3, 4) msl 1 ? maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. this device series incorporates esd protection and exceeds the following ratings: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114. machine model (mm) 200 v per jedec standard: jesd22?a115. 2. latchup current maximum rating: 150 ma per jedec standard: jesd78. 3. lead free: 60?150 sec above 217 c, 40 sec max at peak, 265 c peak. 4. leaded; 60?150 sec above 183 c, 30 sec max at peak, 240 c peak.
NCV4279 http://onsemi.com 4 electrical characteristics (t j = ?40 c t j 125 c, v i = 13.5 v unless otherwise specified) characteristic symbol test conditions min typ max unit regulator output voltage v q 1 ma i q 100 ma; 6 v v i 16 v 4.90 5.00 5.10 v current limit i q ? 150 200 500 ma current consumption; i q = i i ? i q i q i q = 1 ma, ro, so high ? 150 250 a current consumption; i q = i i ? i q i q i q = 10 ma, ro, so high ? 250 450 a current consumption; i q = i i ? i q i q i q = 50 ma, ro, so high ? 2.0 3.0 ma dropout voltage v dr i q = 100 ma (note 5) ? 0.25 0.5 v load regulation vq i q = 5 ma to 100 ma ? 10 20 mv line regulation vq v i = 6 v to 26 v; i q = 1 ma ? 10 30 mv reset generator reset switching threshold v rt ? 4.50 4.65 4.80 v reset adjust switching threshold v rad,jth v q > 3.5 v 1.26 1.35 1.44 v reset output saturation voltage v ro,sat v q < v rt , r ro = 20 k ? 0.1 0.4 v upper delay switching threshold v ud ? 1.4 1.8 2.2 v lower delay switching threshold v ld ? 0.3 0.45 0.60 v saturation voltage on delay capacitor v d,sat v q < v rt ? ? 0.1 v charge current i d v d = 1 v 3.0 6.5 9.5 a delay time l h t d c d = 100 nf 17 28 ? ms delay time h l t t c d = 100 nf ? 1.0 ? s input voltage sense sense threshold high v si , high ? 1.24 1.31 1.38 v sense threshold low v si , low ? 1.16 1.20 1.28 v sense output saturation voltage v so , low v si < 1.20 v; v q > 3 v; r so = 20 k ? 0.1 0.4 v sense input current i si ? ?1.0 0.1 1.0 a 5. dropout voltage = v i ? v q measured when the output voltage has dropped 100 mv from the nominal value obtained at 13.5 v input.
NCV4279 http://onsemi.com 5 figure 2. measuring circuit radj1 v i i i i radj i q v si c d 100 nf v d i d i q v ro v so v radj radj2 c i 470 nf 1000 f i si v q c q 22 f i si d gnd ro so radj q r so r ro figure 3. reset timing diagram v i v q v d v ld v rt v ro,sat v ro t t t t < t rr t rr t d power?on?reset thermal shutdown voltage dip at input undervoltage secondary spike overload at output dv dt i d c d v ud
NCV4279 http://onsemi.com 6 figure 4. sense timing diagram sense input voltage v slhigh v sllow high low t pdsohl t pdsolh t t sense output voltage
NCV4279 http://onsemi.com 7 typical performance characteristics 35 0 v i (v) i q (ma) 10 20 30 40 50 r l = 33 500 0 i q (ma) v dr (mv) 1.7 ?40 0 40 80 120 16 0 t j ( c) v dradj,th , (v) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 3.2 ?40 0 40 80 120 16 0 t j ( c) v d , (v) v i = 13.5 v 0 2 4 6 8 10 12 14 16 ?40 0 40 80 120 160 figure 5. charge current i d ,c vs. temperature t j figure 6. switching voltage v ud and v ld vs. temperature t j figure 7. drop voltage v dr vs. output current i q t j ( c) i d,c . ( a) v i = 13.5 v v d = 1.0 v 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 v ud v ld figure 8. reset adjust switching threshold v radj,th vs. temperature t j 400 300 200 100 0 30 60 90 120 150 180 t j = 25 c t j = ?40 c t j = 125 c 12 024681 0 v i (v) v q , (v) r l = 50 r l = 200 r l = 100 figure 9. current consumption i q vs. input voltage v i figure 10. output voltage v q vs. input voltage v i 10 8 6 4 2 0 r l = 50 30 25 20 15 10 5 0
NCV4279 http://onsemi.com 8 typical performance characteristics 350 0 v i (v) i q (mv) 10 20 30 40 50 t j = 25 c 5.2 ?40 0 40 80 120 160 t j ( c) v i = 13.5 v 1.6 ?40 0 40 80 120 160 t j ( c) v si , (v) v i = 13.5 v figure 11. sense threshold v si vs. temperature t j figure 12. output voltage v q vs. temperature t j figure 13. output current i q vs. input voltage v i 1.5 1.4 1.3 1.2 1.1 1.0 sense output high sense output low 2.1 5.0 4.9 4.8 4.7 4.6 v q , (v) 300 250 200 150 100 50 0 t j = 125 c
NCV4279 http://onsemi.com 9 typical performance characteristics 250 6 v i (v) i q , ( a) i q = 100 a 8 1012 14 161820 2224 26 200 150 100 50 0 7 6 v i (v) i q , (ma) i q = 100 ma 1.6 01020304050 i q (ma) i q , (ma) v i = 13.5 v t j = 25 c 0 2 4 6 8 10 12 0 20406080100120 figure 14. current consumption i q vs. output current i q figure 15. current consumption i q vs. output current i q figure 16. current consumption i q vs. input voltage v i i q (ma) i q , (ma) v i = 13.5 v t j = 25 c 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 i q = 50 ma i q = 10 ma 6 5 4 3 2 1 0 8 1012 14 161820 2224 26 t j = 25 c t j = 25 c figure 17. current consumption i q vs. input voltage v i
NCV4279 http://onsemi.com 10 application description output regulator the output is controlled by a precision trimmed reference. the pnp output has drive quiescent current control for regulation while the input voltage is low, preventing over saturation. current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits. reset output (ro) a reset signal, reset output, ro, (low voltage) is generated as the ic powers up. after the output voltage v q increases above the reset threshold voltage v rt , the delay timer d is started. when the voltage on the delay timer v d passes v ud , the reset signal ro goes high. a discharge of the delay timer v d is started when v q drops and stays below the reset threshold voltage v rt . when the voltage of the delay timer v d drops below the lower threshold voltage v ld the reset output voltage v ro is brought low to reset the processor. the reset output ro is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic, thereby guaranteeing that ro is valid for v q as low as 1.0 v. reset adjust (r adj ) the reset threshold v rt can be decreased from a typical value of 4.65 v to as low as 3.5 v by using an external voltage divider connected from the q lead to the pin radj, as shown in figure 18. the resistor divider keeps the voltage above the v radj,th (typical 1.35 v) for the desired input voltages, and overrides the internal threshold detector. adjust the voltage divider according to the following relationship: v rt v radj, th (r adj1 r adj2 ) r adj2 (eq. 1) if the reset adjust option is not needed, the r adj pin should be connected to gnd causing the reset threshold to go to its default value (typically 4.65 v). reset delay (d) the reset delay circuit provides a delay (programmable by capacitor c d ) on the reset output lead ro. the delay lead d provides charge current i d (typically 6.5 a) to the external delay capacitor c d during the following times: 1. during powerup (once the regulation threshold has been exceeded). 2. after a reset event has occurred and the device is back in regulation. the delay capacitor is set to discharge when the regulation (v rt , reset threshold voltage) has been violated. when the delay capacitor discharges to v ld , the reset signal ro pulls low. setting the delay time the delay time is set by the delay capacitor c d and the charge current i d . the time is measured by the delay capacitor voltage charging from the low level of v dsat to the higher level v ud . the time delay follows the equation: t d [c d (v ud v dsat )] i d (eq. 2) example: using c d = 100 nf. use the typical value for v dsat = 0.1 v. use the typical value for v ud = 1.8 v. use the typical value for delay charge current i d = 6.5 a. t d [100 nf (1.8 0.1 v)] 6.5 a 26.2 ms (eq. 3) q gnd i r adj NCV4279 c q ** 10 f ro 0.1 f microprocessor d c d v bat v dd so figure 18. application diagram si i/o i/o r adj2 r adj1 r si1 r si2 c i * *c i required if regulator is located far from the power supply filter. ** c q required for stability. cap must operate at minimum temperature expected. r so r ro
NCV4279 http://onsemi.com 11 sense input (si) / sense output (so) voltage monitor an on?chip comparator is available to provide early warning to the microprocessor of a possible reset signal. the output is from an open collector driver. the reset signal typically turns the microprocessor of f instantaneously. this can cause unpredictable results with the microprocessor. the signal received from the so pin will allow the microprocessor time to complete its present task before shutting down. this function is performed by a comparator referenced to the band gap voltage. the actual trip point can be programmed externally using a resistor divider to the input monitor si (figure 18). the values for r si1 and r si2 are selected for a typical threshold of 1.20 v on the si pin. signal output figure 19 shows the so monitor timing waveforms as a result of the circuit depicted in figure 18. as the output voltage (v q ) falls, the monitor threshold (v silow ), is crossed. this causes the voltage on the so output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. t wa r n i n g is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal. figure 19. so warning waveform time diagram v q si v ro v silow t warning so stability considerations the input capacitor c i in figure 18 is necessary for compensating input line reactance. possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1.0 in series with c i. the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25 c to ?40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c q shown in figure 18 should work for most applications; however, it is not necessarily the optimized solution. stability is guaranteed at values c q = 10 f and an esr = 10 within the operating temperature range. actual limits are shown in a graph in the typical data section. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 18) is: p d(max) [v i(max) v q(min) ]i q(max) v i(max) i q (eq. 4) where: v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: (eq. 5) r ja = (150 c ? t a ) / p d the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. the current flow and voltages are shown in the measurement circuit diagram. heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (eq. 6) where: r jc = the junction?to?case thermal resistance, r cs = the case?to?heat sink thermal resistance, and r sa = the heat sink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in data sheets of heatsink manufacturers. thermal, mounting, and heatsinking considerations are discussed in the on semiconductor application note an1040/d, available on the on semiconductor website.
NCV4279 http://onsemi.com 12 ordering information device output voltage package shipping ? NCV4279d1 5.0 v so?8 98 units/rail NCV4279d1g so?8 (pb?free) NCV4279d1r2 so?8 2500 tape & reel NCV4279d1r2g so?8 (pb?free) NCV4279d2 so?14 55 units/rail NCV4279d2g so?14 (pb?free) NCV4279d2r2 so?14 2500 tape & reel NCV4279d2r2g so?14 (pb?free) ?for information on tape and reel specifications,including part orientation and tape sizes, please refer to our tape and reel p ackaging specifications brochure, brd8011/d.
NCV4279 http://onsemi.com 13 package dimensions so?8 d suffix case 751?07 issue af seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches
scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
NCV4279 http://onsemi.com 14 package dimensions so?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NCV4279/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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